Invention Grant
- Patent Title: Method for making self-aligned barrier for metal vias In-Situ during a metal halide pre-clean and associated interconnect structure
-
Application No.: US16721762Application Date: 2019-12-19
-
Publication No.: US11227794B2Publication Date: 2022-01-18
- Inventor: Sung-Li Wang , Shuen-Shin Liang , Yu-Yun Peng , Fang-Wei Lee , Chia-Hung Chu , Mrunal Abhijith Khaderbad , Keng-Chu Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/306 ; H01L23/522 ; H01L21/285 ; H01L21/02 ; H01L23/532

Abstract:
A multi-layer interconnect structure with a self-aligning barrier structure and a method for fabricating the same is disclosed. For example, the method includes forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure, pre-cleaning the via with a metal halide, forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide, and depositing a second metal in the via on top of the barrier structure.
Public/Granted literature
- US20210193511A1 METHOD FOR MAKING SELF-ALIGNED BARRIER FOR METAL VIAS Public/Granted day:2021-06-24
Information query
IPC分类: