公开(公告)号：US12046634B2

公开(公告)日：2024-07-23

申请号：US18158148

申请日：2023-01-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Wei Chang ,  Shuen-Shin Liang ,  Sung-Li Wang ,  Hsu-Kai Chang ,  Chia-Hung Chu ,  Chien-Shun Liao ,  Yi-Ying Liu

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/0665 ,  H01L29/1033 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742

摘要： A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

公开(公告)号：US11894437B2

公开(公告)日：2024-02-06

申请号：US17320553

申请日：2021-05-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shuen-Shin Liang ,  Chih-Chien Chi ,  Chien-Shun Liao ,  Keng-Chu Lin ,  Kai-Ting Huang ,  Sung-Li Wang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Hsu-Kai Chang ,  Cheng-Wei Chang

IPC分类号： H01L29/45 ,  H01L23/535 ,  H01L23/532 ,  H01L29/78 ,  H01L21/768

CPC分类号： H01L29/45 ,  H01L21/7684 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76882 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/53209 ,  H01L29/7851

摘要： The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

公开(公告)号：US20220367662A1

公开(公告)日：2022-11-17

申请号：US17876313

申请日：2022-07-28

申请人： Taiwan Semiconductor Manufacturing, Co., Ltd.

发明人： Shuen-Shin Liang ,  Chun-I Tsai ,  Chih-Wei Chang ,  Chun-Hsien Huang ,  Hung-Yi Huang ,  Keng-Chu Lin ,  Ken-Yu Chang ,  Sung-Li Wang ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC分类号： H01L29/45 ,  H01L23/535 ,  H01L21/768

摘要： The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

公开(公告)号：US20220320338A1

公开(公告)日：2022-10-06

申请号：US17806541

申请日：2022-06-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Mrunal A. Khaderbad ,  Keng-Chu Lin ,  Sung-Li Wang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768

摘要： A structure includes a transistor including a first source/drain region, a source/drain contact plug over and electrically coupling to the first source/drain region, and a via over and contacting the source/drain contact plug. The via has a bottom portion having a first length, and an upper portion having a second length. The first length is greater than the second length. Both of the first length and the second length are measured in a same direction parallel to a top surface of the source/drain contact plug.

公开(公告)号：US11211383B2

公开(公告)日：2021-12-28

申请号：US16927799

申请日：2020-07-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Sung-Li Wang ,  Pang-Yen Tsai ,  Yasutoshi Okuno

IPC分类号： H01L27/092 ,  H01L29/45 ,  H01L21/8238 ,  H01L29/08 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L21/321 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

摘要： A semiconductor device includes first and second epitaxial structures, first and second top metal alloy layers, and first and second bottom metal alloy layers. The first and second epitaxial structures have different cross sections. The first and second top metal alloy layers are respectively in contact with the first and second epitaxial structures. The first and second bottom metal alloy layers are respectively in contact with the first and second epitaxial structures and respectively under the first and second top metal alloy layers. The first top metal alloy layer and the first bottom metal alloy layer are made of different materials.

公开(公告)号：US11201232B2

公开(公告)日：2021-12-14

申请号：US16931590

申请日：2020-07-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Mrunal A. Khaderbad ,  Sung-Li Wang ,  Yasutoshi Okuno

IPC分类号： H01L29/66 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/285 ,  H01L29/08

摘要： Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a source/drain structure formed adjacent to the gate structure in the substrate and a contact formed over the source/drain structure. The semiconductor structure further includes a metal-containing layer formed over the contact and a dielectric layer covering the gate structure and the metal-containing layer. The semiconductor structure further includes a first conductive structure formed through dielectric layer and the metal-containing layer and landing on the contact. In addition, a bottom surface of the metal-containing layer is higher than a top surface of the gate structure.

公开(公告)号：US20210233861A1

公开(公告)日：2021-07-29

申请号：US16936335

申请日：2020-07-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsu-Kai Chang ,  Keng-Chu Lin ,  Sung-Li Wang ,  Shuen-Shin Liang ,  Chia-Hung Chu

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L21/768

摘要： The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

公开(公告)号：US20210193816A1

公开(公告)日：2021-06-24

申请号：US16721352

申请日：2019-12-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Peng-Wei Chu ,  Ding-Kang Shih ,  Sung-Li Wang ,  Yasutoshi Okuno

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/45 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08

摘要： The structure of a semiconductor device with dual silicide contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming first and second fin structures on a substrate, forming first and second epitaxial regions on the first and second fin structures, respectively, forming first and second contact openings on the first and second epitaxial regions, respectively, selectively forming an oxide capping layer on exposed surfaces of the second epitaxial region, selectively forming a first metal silicide layer on exposed surfaces of the first epitaxial region, removing the oxide capping layer, and forming first and second conductive regions on the metal silicide layer and on the exposed surfaces of the second epitaxial region, respectively. The first metal silicide layer includes a first metal. The first and second conductive regions includes a second metal different from the first metal.

公开(公告)号：US20240347611A1

公开(公告)日：2024-10-17

申请号：US18750737

申请日：2024-06-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ding-Kang Shih ,  Sung-Li Wang ,  Pang-Yen Tsai

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/76202 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848 ,  H01L29/785 ,  H01L21/823871 ,  H01L29/665 ,  H01L29/66545

摘要： Examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. In some examples, a substrate is received having a source/drain feature disposed on the substrate. The source/drain feature includes a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. The oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. In some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.

公开(公告)号：US12074061B2

公开(公告)日：2024-08-27

申请号：US17407083

申请日：2021-08-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sheng-Tsung Wang ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Sung-Li Wang ,  Chih-Hao Wang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/76846 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

摘要： A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.