Invention Grant
- Patent Title: Planar slab vias for integrated circuit interconnects
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Application No.: US16824366Application Date: 2020-03-19
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Publication No.: US11239156B2Publication Date: 2022-02-01
- Inventor: Elijah Karpov , Manish Chandhok , Nafees Kabir
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/522 ; H01L23/528 ; H01L23/532 ; H01L21/768

Abstract:
Integrated circuitry comprising devices electrically coupled through a plurality of interconnect levels in which lines of a first and second interconnect level are coupled through a planar slab via. An interconnect line may include a horizontal line segment within one of the first or second interconnect levels, and the slab via may be a vertical line segment between the first and second interconnect levels. A planar slab via may comprise one or more layers of conductive material, which have been deposited upon a planarized substrate material that lacks any features that the conductive material must fill. A planar slab via may be subtractively defined concurrently with a horizontal line of one or both of the first or second interconnect levels.
Public/Granted literature
- US20210296231A1 PLANAR SLAB VIAS FOR INTEGRATED CIRCUIT INTERCONNECTS Public/Granted day:2021-09-23
Information query
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