Multilayer pillar for reduced stress interconnect and method of making same

Invention Grant

US11244917B2 Multilayer pillar for reduced stress interconnect and method of making same 有权

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Patent Title: Multilayer pillar for reduced stress interconnect and method of making same
Application No.: US16502648

Application Date: 2019-07-03
Publication No.: US11244917B2

Publication Date: 2022-02-08
Inventor: Virendra R. Jadhav , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Applicant Address: US NY Armonk
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Current Assignee Address: US NY Armonk
Agency: Roberts Calderon Safran & Cole, P.C.
Agent L. Jeffrey Kelly; Andrew M. Calderon
Main IPC: H01L23/00
IPC: H01L23/00

Multilayer pillar for reduced stress interconnect and method of making same

Abstract:

A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Public/Granted literature

US20190326243A1 MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME Public/Granted day:2019-10-24

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L23/00	半导体或其他固态器件的零部件（H01L25/00优先）