Invention Grant
- Patent Title: Sacrificial dielectric for lithographic via formation to enable via scaling in high density interconnect packaging
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Application No.: US15857332Application Date: 2017-12-28
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Publication No.: US11264346B2Publication Date: 2022-03-01
- Inventor: Kristof Darmawikarta , Sri Ranga Sai Boyapati , Hiroki Tanaka , Robert A. May
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP.
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/48 ; H01L23/538 ; H01L23/498
Abstract:
An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.
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Information query
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