公开(公告)号：US11908821B2

公开(公告)日：2024-02-20

申请号：US17563995

申请日：2021-12-28

申请人： Intel Corporation

发明人： Kristof Darmawikarta ,  Sri Ranga Sai Boyapati ,  Hiroki Tanaka ,  Robert A. May

IPC分类号： H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L24/19 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/20 ,  H01L2224/18

摘要： An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.

公开(公告)号：US11908802B2

公开(公告)日：2024-02-20

申请号：US17842600

申请日：2022-06-16

申请人： Intel Corporation

发明人： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Kristof Darmawikarta ,  Robert A. May ,  Sri Ranga Sai Boyapati

IPC分类号： H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/00 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5383 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5384 ,  H01L24/13 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/381 ,  H01L2224/97 ,  H01L2224/81

摘要： An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

公开(公告)号：US11862619B2

公开(公告)日：2024-01-02

申请号：US16649923

申请日：2017-12-29

申请人： Intel Corporation

发明人： Srinivas Pietambaram ,  Robert Alan May ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Rahul N. Manepalli ,  Sri Ranga Sai Boyapati

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0652 ,  H01L24/14 ,  H01L2224/1403

摘要： Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

公开(公告)号：US11430740B2

公开(公告)日：2022-08-30

申请号：US16474026

申请日：2017-03-29

申请人： Intel Corporation

发明人： Robert Alan May ,  Islam A. Salama ,  Sri Ranga Sai Boyapati ,  Sheng Li ,  Kristof Darmawikarta ,  Robert L. Sankman ,  Amruthavalli Pallavi Alur

IPC分类号： H01L23/52 ,  H01L23/31 ,  H01L25/07 ,  H01L25/11 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

摘要： Microelectronic devices with an embedded die substrate on an interposer are described. For example, a microelectronic device includes a substrate housing an embedded die. At least one surface die is retained above a first outermost surface of the substrate. An interposer is retained proximate a second outermost surface of the substrate.

公开(公告)号：US11309192B2

公开(公告)日：2022-04-19

申请号：US16000205

申请日：2018-06-05

申请人： Intel Corporation

发明人： Kristof Kuwawi Darmawikarta ,  Robert May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram ,  Chung Kwang Christopher Tan ,  Aleksandar Aleksov

IPC分类号： H01L21/48 ,  H01L23/498

摘要： Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.

公开(公告)号：US11270959B2

公开(公告)日：2022-03-08

申请号：US15933599

申请日：2018-03-23

申请人： Intel Corporation

发明人： Kirstof Darmawikarta ,  Srinivas Pietambaram ,  Prithwish Chatterjee ,  Sri Ranga Sai Boyapati ,  Wei Lun Jen

IPC分类号： H01L23/64 ,  H01F27/28 ,  H01F1/14 ,  H01F1/34 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01F41/04

摘要： Techniques for fabricating a semiconductor package comprising inductor features and a magnetic film are described. For one technique, fabricating a package includes: forming inductor features comprising a pad and a conductive line on a first build-up layer; forming a raised pad structure on the first build-up layer by fabricating a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other; encapsulating the inductor features and the raised pad structure in a magnetic film; planarizing the magnetic film until top surfaces of the raised pad structure and magnetic film are co-planar; depositing an additional layer on the top surfaces; and forming a via on the raised pad structure by removing portions of the additional layer above the raised pad structure.

公开(公告)号：US11244912B2

公开(公告)日：2022-02-08

申请号：US16481385

申请日：2017-03-30

申请人： Intel Corporation

发明人： Sai Vadlamani ,  Aleksandar Aleksov ,  Rahul Jain ,  Kyu Oh Lee ,  Kristof Kuwawi Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Boyapati ,  Telesphor Kamgaing

IPC分类号： H01L21/48 ,  H01L23/66 ,  H01L23/498 ,  H01L23/00

摘要： Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.

公开(公告)号：US11101222B2

公开(公告)日：2021-08-24

申请号：US16326679

申请日：2016-09-29

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta ,  Javier Soto Gonzalez ,  Kwangmo Lim

IPC分类号： H01L23/538 ,  H01L23/00

摘要： A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

公开(公告)号：US11043457B2

公开(公告)日：2021-06-22

申请号：US16889735

申请日：2020-06-01

申请人： Intel Corporation

发明人： Amruthavalli Pallavi Alur ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Islam A. Salama ,  Robert L. Sankman

IPC分类号： H01L23/492 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L25/18 ,  H01L23/31 ,  H01L21/66 ,  H01L21/683 ,  H01L25/11

摘要： An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

公开(公告)号：US20210066232A1

公开(公告)日：2021-03-04

申请号：US17098754

申请日：2020-11-16

申请人： Intel Corporation

发明人： Robert Alan May ,  Sri Ranga Sai Boyapati ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Javier Soto Gonzalez ,  Kwangmo Chris Lim ,  Aleksandar Aleksov

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/13 ,  H01L21/48

摘要： Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.