- Patent Title: Fin-type field effect transistor with reduced fin bulge and method
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Application No.: US16942816Application Date: 2020-07-30
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Publication No.: US11264382B2Publication Date: 2022-03-01
- Inventor: Jiehui Shu , Bharat V. Krishnan
- Applicant: GlobalFoundries U.S. Inc.
- Applicant Address: US NY Malta
- Assignee: GlobalFoundries U.S. Inc.
- Current Assignee: GlobalFoundries U.S. Inc.
- Current Assignee Address: US NY Malta
- Agency: Gibb & Riley, LLC
- Agent Francois Pagette
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L29/66 ; H01L29/06 ; H01L29/78 ; H01L29/10 ; H01L21/8234

Abstract:
Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.
Public/Granted literature
- US20210005601A1 FIN-TYPE FIELD EFFECT TRANSISTOR WITH REDUCED FIN BULGE AND METHOD Public/Granted day:2021-01-07
Information query
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