Invention Grant
- Patent Title: Process for fabricating a high-voltage capacitive element, and corresponding integrated circuit
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Application No.: US16802871Application Date: 2020-02-27
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Publication No.: US11271075B2Publication Date: 2022-03-08
- Inventor: Abderrezak Marzaki
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Crowe & Dunlevy
- Priority: FR1902277 20190306
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L49/02 ; H01L27/11521 ; H01L27/11531 ; H01L29/423 ; H01L29/66 ; H01L29/788

Abstract:
A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.
Public/Granted literature
- US20200286986A1 PROCESS FOR FABRICATING A HIGH-VOLTAGE CAPACITIVE ELEMENT, AND CORRESPONDING INTEGRATED CIRCUIT Public/Granted day:2020-09-10
Information query
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