A memory and a signal processing method are provided. The memory includes a latch circuit, a decoding circuit, a storage array, a read circuit, and a write circuit. The storage array includes M rows and N columns of bitcells. The latch circuit is configured to receive a first address and a second address. The decoding circuit is configured to: determine a first bitcell based on the first address, and determine a second bitcell based on the second address. The write circuit is configured to: receive data, and write the data into the first bitcell through a first port of the first bitcell. The read circuit is configured to read, through the first port of the first bitcell, data stored in the first bitcell; and is further configured to read, through a second port of the second bitcell, data stored in the second bitcell. Implementing this application can implement 1R1RW.