- 专利标题: Negative voltage protection for bus interface devices
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申请号: US17151575申请日: 2021-01-18
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公开(公告)号: US11290108B2公开(公告)日: 2022-03-29
- 发明人: Toru Miyamae , Kazuhiro Tomita , Koji Okada
- 申请人: Cypress Semiconductor Corporation
- 申请人地址: US CA San Jose
- 专利权人: Cypress Semiconductor Corporation
- 当前专利权人: Cypress Semiconductor Corporation
- 当前专利权人地址: US CA San Jose
- 主分类号: H03K5/08
- IPC分类号: H03K5/08 ; H03K19/003 ; H03K19/0175
摘要:
A bus interface bus is described. A first logical state is conveyed over the bus by a higher voltage level and a second logical state is conveyed by a lower voltage level. An output stage of the interface includes a power transistor configured to drive the lower voltage level onto the bus to convey the second logical state, and a protective device between the power transistor and the bus. The protective device couples the power transistor to the bus when turned on and limits negative voltage excursions at the power transistor when turned off. A control circuit of the interface is configured to turn on the protective device when the bus voltage is above the lower voltage level and to turn off the protective device when the bus voltage is at or below the lower voltage level.
公开/授权文献
- US20210359685A1 NEGATIVE VOLTAGE PROTECTION FOR BUS INTERFACE DEVICES 公开/授权日:2021-11-18
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