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公开(公告)号：US11362667B1
公开(公告)日：2022-06-14
申请号：US17485082
申请日：2021-09-24
摘要： A device includes a master delay-lock loop (DLL) having a phase frequency detector connected in series with a charge pump that is to generate a control voltage. A slave DLL is coupled to the master DLL and has a delay line including a buffer to receive a slave clock and a series of delay cells coupled between the buffer and an output terminal that is to output a delay clock, the series of delay cells variably controlled by the control voltage. The master DLL and the slave DLL are powered by a power supply that experiences undershoot or overshoot in response to a load transient. A dummy load is coupled between the delay line of the slave DLL and an output of the power supply, the dummy load including an exclusive OR gate that receives, as inputs, a first output of the buffer and the delay clock.
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公开(公告)号：US11290108B2
公开(公告)日：2022-03-29
申请号：US17151575
申请日：2021-01-18
发明人： Toru Miyamae , Kazuhiro Tomita , Koji Okada
IPC分类号： H03K5/08 , H03K19/003 , H03K19/0175
摘要： A bus interface bus is described. A first logical state is conveyed over the bus by a higher voltage level and a second logical state is conveyed by a lower voltage level. An output stage of the interface includes a power transistor configured to drive the lower voltage level onto the bus to convey the second logical state, and a protective device between the power transistor and the bus. The protective device couples the power transistor to the bus when turned on and limits negative voltage excursions at the power transistor when turned off. A control circuit of the interface is configured to turn on the protective device when the bus voltage is above the lower voltage level and to turn off the protective device when the bus voltage is at or below the lower voltage level.
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公开(公告)号：US10484103B2
公开(公告)日：2019-11-19
申请号：US16392405
申请日：2019-04-23
发明人： Kazuhiro Tomita , Masuo Inui
摘要： An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.
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公开(公告)号：US20180276179A1
公开(公告)日：2018-09-27
申请号：US15941549
申请日：2018-03-30
发明人： Akihiro Suzuki , Masami Nakashima , Masuo Inui , Koji Okada , Takeo Zaitsu , Takashi Shimizu , Shinichi Yamamoto , Kazuhiro Tomita , Susumu Kuroda
IPC分类号： G06F13/42 , G06F1/12 , G06F13/40 , G06F1/08 , G06F13/364
CPC分类号： G06F13/4291 , G06F1/04 , G06F1/08 , G06F1/10 , G06F1/12 , G06F1/3237 , G06F1/3287 , G06F13/364 , G06F13/4018 , H03K5/1565
摘要： An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus. The device comprises a transceiver configured to: detect a baud rate clock signal and a phase difference between the baud rate clock signal and an input data signal that was generated asynchronously from the baud rate clock signal; obtain a timing from an edge of the baud rate clock signal based the phase difference; capture a value of the input data signal at the timing; and transmit the captured value as an output data signal over the CXPI bus.
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公开(公告)号：US10063325B2
公开(公告)日：2018-08-28
申请号：US15449558
申请日：2017-03-03
发明人： Kazuhiro Tomita , Masuo Inui
IPC分类号： H04B15/02 , H04B1/3822 , H04L7/00
CPC分类号： H04B15/02 , H04B1/3822 , H04B15/005 , H04L7/0012 , H04L7/0037 , H04L12/40006 , H04L25/4902 , H04L25/4906
摘要： An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.
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公开(公告)号：US09971731B2
公开(公告)日：2018-05-15
申请号：US15374529
申请日：2016-12-09
发明人： Akihiro Suzuki , Masami Nakashima , Masuo Inui , Koji Okada , Takeo Zaitsu , Takashi Shimizu , Shinichi Yamamoto , Kazuhiro Tomita , Susumu Kuroda
IPC分类号： G06F1/12 , G06F13/42 , G06F13/364 , G06F1/08 , G06F13/40
CPC分类号： G06F13/4291 , G06F1/04 , G06F1/08 , G06F1/10 , G06F1/12 , G06F1/3237 , G06F1/3287 , G06F13/364 , G06F13/4018 , H03K5/1565
摘要： An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a CXPI communication network; and an adjusting unit configured to adjust a duty width of the first clock.
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公开(公告)号：US20210357353A1
公开(公告)日：2021-11-18
申请号：US17347282
申请日：2021-06-14
发明人： Akihiro Suzuki , Masami Nakashima , Masuo Inui , Koji Okada , Takeo Zaitsu , Takashi Shimizu , Shinichi Yamamoto , Kazuhiro Tomita , Susumu Kuroda
IPC分类号： G06F13/42 , H03K5/156 , G06F13/364 , G06F1/3287 , G06F1/04 , G06F1/08 , G06F1/3237 , G06F1/10 , G06F1/12 , G06F13/40
摘要： An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus as a slave node. The device comprises a transceiver configured to: generate a first signal by delaying an inverted signal of a transmission data signal: generate a second signal based on the transmission data signal, where the second signal has a low slew rate: selectively output the first signal or the second signal as a third signal, in response to a selector signal: and generate a clock signal in response to the third signal, where the clock signal is at a high level when the third signal is at a low level, and where the clock signal is at the low level when the third signal is at the high level.
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公开(公告)号：US10651952B2
公开(公告)日：2020-05-12
申请号：US16655043
申请日：2019-10-16
发明人： Kazuhiro Tomita , Masuo Inui
摘要： In an example embodiment, a communication system provides a clock extension peripheral interface (CXPI) communication bus that is coupled to a master node and a plurality of slave nodes. The master node is configured to transmit a reference clock signal on the CXPI communication bus. Each slave node of the plurality of slave nodes is configured to receive the reference clock signal from the CXPI communication bus and to transmit and receive data to and from the CXPI communication bus based on the reference clock signal.
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公开(公告)号：US20170199840A1
公开(公告)日：2017-07-13
申请号：US15374529
申请日：2016-12-09
发明人： Akihiro Suzuki , Masami Nakashima , Masuo Inui , Koji Okada , Takeo Zaitsu , Takashi Shimizu , Shinichi Yamamoto , Kazuhiro Tomita , Susumu Kuroda
IPC分类号： G06F13/42 , G06F1/08 , G06F13/40 , G06F13/364
CPC分类号： G06F13/4291 , G06F1/04 , G06F1/08 , G06F1/10 , G06F1/12 , G06F1/3237 , G06F1/3287 , G06F13/364 , G06F13/4018 , H03K5/1565
摘要： An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a CXPI communication network; and an adjusting unit configured to adjust a duty width of the first clock.
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公开(公告)号：US20210359685A1
公开(公告)日：2021-11-18
申请号：US17151575
申请日：2021-01-18
发明人： Toru Miyamae , Kazuhiro Tomita , Koji Okada
IPC分类号： H03K19/003 , H03K19/0175
摘要： A bus interface bus is described. A first logical state is conveyed over the bus by a higher voltage level and a second logical state is conveyed by a lower voltage level. An output stage of the interface includes a power transistor configured to drive the lower voltage level onto the bus to convey the second logical state, and a protective device between the power transistor and the bus. The protective device couples the power transistor to the bus when turned on and limits negative voltage excursions at the power transistor when turned off. A control circuit of the interface is configured to turn on the protective device when the bus voltage is above the lower voltage level and to turn off the protective device when the bus voltage is at or below the lower voltage level.
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