Invention Grant
- Patent Title: Method for testing a high voltage transistor with a field plate
-
Application No.: US16444936Application Date: 2019-06-18
-
Publication No.: US11302785B2Publication Date: 2022-04-12
- Inventor: Ramana Tadepalli , Chang Soo Suh
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Ronald O. Neerings; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L21/66
- IPC: H01L21/66 ; G01R31/26 ; H01L21/44 ; H01L21/48 ; H01L29/40 ; H01L29/78 ; H01L21/768 ; H01L23/528 ; H01L23/00 ; H01L23/31 ; H01L29/778 ; H01L29/20 ; H01L29/24

Abstract:
In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.
Information query
IPC分类: