Inference operation method and controlling circuit of 3D NAND artificial intelligence accelerator
Abstract:
An inference operation method and a controlling circuit of a 3D NAND artificial intelligence accelerator are provided. The 3D NAND artificial intelligence accelerator includes a plurality of memory cells, a plurality of bit lines, a plurality of word lines and a plurality of string selecting line groups each of which includes at least one string selecting line. The inference operation method includes the following steps: The patterns are inputted to the bit lines. The word lines are switched to switch the filters. The string selecting line groups are switched to switch the filters. In a word line pioneering scheme and a string selecting line group pioneering scheme, when the patterns inputted to each of the bit lines are switched, any one of the word lines is not switched and any one of the string selecting line groups is not switched.
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