A method for manufacturing a vertical field effect transistor (VFET) device may include: providing an intermediate VFET structure including a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region; forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other; filling the shallow trench and a space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above a level of a top surface of the doped layer, except in the shallow trench, such that a shallow trench isolation (STI) structure having a top surface to be at or above a level of the top surface of the doped layer is formed in the shallow trench; forming a plurality of gate structures on the fin structures, respectively; and forming a top S/D region above the fin structures.