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公开(公告)号：US11804540B2
公开(公告)日：2023-10-31
申请号：US18071168
申请日：2022-11-29
发明人： Hwi Chan Jun , Min Gyu Kim , Gil-Hwan Son
IPC分类号： H01L29/66 , H01L29/78 , H01L29/417 , H01L21/285
CPC分类号： H01L29/66666 , H01L21/28512 , H01L29/41741 , H01L29/7827
摘要： A vertical field effect transistor (VFET) device and a method of manufacturing the same are provided. The method includes: (a) providing an intermediate VFET structure comprising a substrate, and fin structures, gate structures and bottom epitaxial layers on the substrate, the gate structures being formed on the fin structures, respectively, each fin structure comprising a fin and a mask thereon, and the bottom epitaxial layers; (b) filling interlayer dielectric (ILD) layers between and at sides of the gate structures; (c) forming an ILD protection layer on the ILD layers, respectively, the ILD protection layer having upper portions and lower portions, and comprising a material preventing oxide loss at the ILD layers; (d) removing the fin structures, the gate structures and the ILD protection layer above the lower portion of the ILD protection layer; (e) removing the masks of the fin structures and top portions of the gate structures so that top surfaces of the fin structures and top surfaces of the gate structures after the removing are lower than top surfaces of the ILD layers; (f) forming top spacers on the gate structures of which the top portions are removed, and top epitaxial layers on the fin structures of which the masks are removed; and (g) forming a contact structure connected to the top epitaxial layers.
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公开(公告)号：US11295986B2
公开(公告)日：2022-04-05
申请号：US16724702
申请日：2019-12-23
发明人： Min Gyu Kim , Sa Hwan Hong
IPC分类号： H01L21/8234
摘要： Vertical field-effect transistor (VFET) devices and methods of forming the VFET devices are provided. The methods may include forming a first channel region and a second channel region on a substrate, forming a recess in the substrate between the first and second channel regions by removing a portion of the liner and a portion of the substrate, forming a bottom source/drain region in the recess of the substrate, forming a capping layer on the bottom source/drain region, removing the liner and the capping layer, forming a spacer on the substrate and the bottom source/drain region, and forming a gate structure on side surfaces of the first and second channel regions.
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公开(公告)号：US11282752B2
公开(公告)日：2022-03-22
申请号：US17035857
申请日：2020-09-29
发明人： Hwi Chan Jun , Min Gyu Kim
IPC分类号： H01L21/8234
摘要： Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.
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4.发明申请公开(公告)号：US20200218870A1
公开(公告)日：2020-07-09
申请号：US16534574
申请日：2019-08-07
发明人： Yong Il Kwon , Min Gyu Kim , Sun Kwon Kim , Seong Il Park , Jong Sung Lee , Hee Bum Lee
摘要： A fingerprint recognition device includes a display, a touch sensor panel (TSP) which senses a touch, and a fingerprint recognition integrated circuit (FPIC) which scans a fingerprint. The FPIC includes a pixel including a photoelectric element which receives light reflected by the fingerprint, a low noise amplifier (LNA) which outputs a signal voltage by converting an electric charge received from the photoelectric element, and an analog-to-digital converter (ADC) which converts the signal voltage into a digital signal. The ADC includes a variable reference voltage generator which provides a variable reference voltage, a comparator which adds the variable reference voltage to the signal voltage, performs correlated double sampling on the result of the addition, and outputs a comparison signal by comparing the result of the correlated double sampling with a ramp voltage, and a counter which outputs the digital signal by counting the comparison signal.
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公开(公告)号：US11915982B2
公开(公告)日：2024-02-27
申请号：US17669452
申请日：2022-02-11
发明人： Hwi Chan Jun , Min Gyu Kim
IPC分类号： H01L21/8234
CPC分类号： H01L21/823487 , H01L21/823437 , H01L21/823481
摘要： Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.
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公开(公告)号：US11048364B2
公开(公告)日：2021-06-29
申请号：US16549714
申请日：2019-08-23
发明人： Yong Jin Park , Min Gyu Kim , Sun Kwon Kim , Jong Bin Moon , Young Kil Choi , Yoon Kyung Choi
摘要： A method for acquiring capacitance of a capacitive touch panel includes acquiring a selected capacitance value at a selected point among a plurality of points at which a plurality of capacitances are present, in the capacitive touch panel, determining the selected capacitance value as a reference capacitance value, and performing a multi-driving using a balanced code, and acquiring a capacitance value from at least one point among the plurality of points using the reference capacitance value.
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公开(公告)号：US20220415906A1
公开(公告)日：2022-12-29
申请号：US17577120
申请日：2022-01-17
发明人： Sung Il Park , Jae Hyun Park , Min Gyu Kim , Do Young Choi , Dae Won Ha
IPC分类号： H01L27/11 , H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66
摘要： A semiconductor memory device and a method for manufacturing the same. The semiconductor memory device may include a substrate, a first lower wire pattern and a first upper wire pattern stacked on the substrate, and spaced apart from each other; a second lower wire pattern and a second upper wire pattern stacked on the substrate, spaced apart from each other, and spaced apart from the first lower and upper wire patterns; a first gate line surrounding the first lower wire pattern and the first upper wire pattern; a second gate line surrounding the second lower wire pattern and the second upper wire pattern and spaced apart from the first gate line; a first lower source/drain area; a first upper source/drain area; and a first overlapping contact that electrically connects the first lower source/drain area, the first upper source/drain area and the second gate line to each other.
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公开(公告)号：US11309405B2
公开(公告)日：2022-04-19
申请号：US16846813
申请日：2020-04-13
发明人： Hwi Chan Jun , Min Gyu Kim , Seon Bae Kim
IPC分类号： H01L29/66 , H01L29/78 , H01L29/423 , H01L21/8234
摘要： A method for manufacturing a vertical field effect transistor (VFET) device may include: providing an intermediate VFET structure including a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region; forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other; filling the shallow trench and a space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above a level of a top surface of the doped layer, except in the shallow trench, such that a shallow trench isolation (STI) structure having a top surface to be at or above a level of the top surface of the doped layer is formed in the shallow trench; forming a plurality of gate structures on the fin structures, respectively; and forming a top S/D region above the fin structures.
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9.发明授权公开(公告)号：US11244139B2
公开(公告)日：2022-02-08
申请号：US16534574
申请日：2019-08-07
发明人： Yong Il Kwon , Min Gyu Kim , Sun Kwon Kim , Seong Il Park , Jong Sung Lee , Hee Bum Lee
摘要： A fingerprint recognition device includes a display, a touch sensor panel (TSP) which senses a touch, and a fingerprint recognition integrated circuit (FPIC) which scans a fingerprint. The FPIC includes a pixel including a photoelectric element which receives light reflected by the fingerprint, a low noise amplifier (LNA) which outputs a signal voltage by converting an electric charge received from the photoelectric element, and an analog-to-digital converter (ADC) which converts the signal voltage into a digital signal. The ADC includes a variable reference voltage generator which provides a variable reference voltage, a comparator which adds the variable reference voltage to the signal voltage, performs correlated double sampling on the result of the addition, and outputs a comparison signal by comparing the result of the correlated double sampling with a ramp voltage, and a counter which outputs the digital signal by counting the comparison signal.
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公开(公告)号：US11141688B2
公开(公告)日：2021-10-12
申请号：US16171788
申请日：2018-10-26
发明人： Jae Hun Hur , Jae Kwon Ko , Han Taek Kwak , Min Gyu Kim
IPC分类号： B01D46/44 , F24F8/10 , B01D46/00 , F24F11/38 , F24F110/50
摘要： An air cleaning system having at least one dust sensor and a method for controlling the air cleaning system may improve accuracy of dust sensors through linkage control of the dust sensors, and may normally operate a faulty air cleaner using dust sensors of the remaining communicating air cleaners other than the faulty air cleaner even when any one of the dust sensors fails to operate. The air cleaning system may select a master dust sensor through linkage control of the dust sensors, and may operate the plurality of air cleaners only using sensor information of the master dust sensor. Therefore, the air cleaning system may stop operation of the remaining dust sensors other than the master dust sensor, may reduce measurement noise produced by the dust sensors and power consumption, and may increase a lifetime of the dust sensors.
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