Invention Grant
- Patent Title: Defect detection during program verify in a memory sub-system
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Application No.: US15929439Application Date: 2020-05-01
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Publication No.: US11315647B2Publication Date: 2022-04-26
- Inventor: Pinchou Chiang , Arvind Muralidharan , James I. Esteves , Michele Piccardi , Theodore T. Pekny
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/04 ; G11C16/10

Abstract:
A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.
Public/Granted literature
- US20210343351A1 DEFECT DETECTION DURING PROGRAM VERIFY IN A MEMORY SUB-SYSTEM Public/Granted day:2021-11-04
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