Invention Grant
- Patent Title: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof
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Application No.: US16678695Application Date: 2019-11-08
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Publication No.: US11329042B2Publication Date: 2022-05-10
- Inventor: Chia-Hao Pao , Chih-Hsuan Chen , Lien Jung Hung , Shih-Hao Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/78 ; H01L29/66 ; H01L21/8238 ; H01L29/423

Abstract:
Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.
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