Invention Grant
- Patent Title: Error remapping
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Application No.: US16823908Application Date: 2020-03-19
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Publication No.: US11335430B2Publication Date: 2022-05-17
- Inventor: Christopher Haywood
- Applicant: Rambus Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: The Neudeck Law Firm, LLC
- Main IPC: G11C29/44
- IPC: G11C29/44 ; G11C29/18 ; G11C29/12 ; G11C7/22 ; G11C29/00

Abstract:
Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.
Public/Granted literature
- US20200312420A1 ERROR REMAPPING Public/Granted day:2020-10-01
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