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公开(公告)号：US20250139029A1
公开(公告)日：2025-05-01
申请号：US18941090
申请日：2024-11-08
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Christopher Haywood
Abstract: In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.
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公开(公告)号：US20240111449A1
公开(公告)日：2024-04-04
申请号：US18367789
申请日：2023-09-13
Applicant: RAMBUS INC.
Inventor： Christopher Haywood , Frederick A. Ware
IPC: G06F3/06
CPC classification number: G06F3/0656 , G06F3/061 , G06F3/0673
Abstract: A cascaded memory system includes a memory module having a primary interface coupled to a memory controller via a first communication channel and a secondary interface coupled to a second memory module via a second communication channel. The first memory module buffers and repeats signals received on the primary and secondary interfaces to enable communications between the memory controller and the secondary memory module.
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公开(公告)号：US11609870B2
公开(公告)日：2023-03-21
申请号：US17296532
申请日：2019-11-21
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Christopher Haywood
IPC: G06F13/16 , G06F13/40 , G11C7/10 , G11C5/04 , G11C11/4093 , G11C11/4096
Abstract: In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.
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公开(公告)号：US20230072394A1
公开(公告)日：2023-03-09
申请号：US17897439
申请日：2022-08-29
Applicant: Rambus Inc.
Inventor： Christopher Haywood , Steven C. Woo
IPC: G11C7/10
Abstract: A memory system includes a memory controller, a plurality of serial data buffers, and a plurality of memory devices. The memory controller issues packetized commands and data to the serial data buffers. The serial data buffers each apply a different remapping function to remap an input command address in the packetized commands to respective remapped memory addresses that are different for each serial data buffer. The serial data buffers then issue commands to the memory devices using the remapped addresses. The remapping functions may be designed to mitigate row hammer effects. The serial data buffers may furthermore apply transformations to read and write data to facilitate encryption and decryption.
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公开(公告)号：US11282552B2
公开(公告)日：2022-03-22
申请号：US16831121
申请日：2020-03-26
Applicant: Rambus Inc.
Inventor： Christopher Haywood , David Wang
Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.
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Patent Agency Ranking
公开(公告)号：US20210397570A1
公开(公告)日：2021-12-23
申请号：US17296532
申请日：2019-11-21
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Christopher Haywood
Abstract: In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.
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公开(公告)号：US10896099B2
公开(公告)日：2021-01-19
申请号：US16156953
申请日：2018-10-10
Applicant: Rambus Inc.
Inventor： Shih-ho Wu , Christopher Haywood
Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.
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公开(公告)号：US09570146B1
公开(公告)日：2017-02-14
申请号：US14181422
申请日：2014-02-14
Applicant: Rambus Inc.
Inventor： Christopher Haywood
IPC: G06F13/12 , G06F13/38 , G11C11/406
CPC classification number: G11C7/20 , G11C7/22 , G11C7/227 , G11C11/406 , G11C11/40611
Abstract: A method for operating a DRAM is provided. The method includes initializing a dynamic random access memory (“DRAM”) array from a host controller, which is coupled to the DRAM array. The method includes isolating the dynamic random access memory array from a host controller and allowing a host computer to wait for a selected time period greater than the tRFC to define an alternate access time. The method includes initiating an access command to the DRAM array during the alternate access time.
Abstract translation: 提供了一种用于操作DRAM的方法。 该方法包括从耦合到DRAM阵列的主机控制器初始化动态随机存取存储器（“DRAM”）阵列。 该方法包括从主机控制器隔离动态随机存取存储器阵列并允许主计算机等待大于tRFC的选定时间段以定义备用访问时间。 该方法包括在替代访问时间期间启动对DRAM阵列的访问命令。
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公开(公告)号：US12205669B2
公开(公告)日：2025-01-21
申请号：US18513473
申请日：2023-11-17
Applicant: Rambus Inc.
Inventor： Christopher Haywood , David Wang
Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.
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公开(公告)号：US12204446B2
公开(公告)日：2025-01-21
申请号：US18140441
申请日：2023-04-27
Applicant: Rambus Inc.
Inventor： Evan Lawrence Erickson , Christopher Haywood
IPC: G06F12/02 , G06F12/0891
Abstract: A buffer/interface device of a memory node reads a block of data (e.g., page). As each unit of data (e.g., cache line sized) of the block is read, it is compared against one or more predefined patterns (e.g., all 0's, all 1's, etc.). If the block (page) is only storing one of the predefined patterns, a flag in the page table entry for the block is set to indicate the block is only storing one of the predefined patterns. The physical memory the block was occupying may then be deallocated so other data may be stored using those physical memory addresses.
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