Invention Grant
- Patent Title: Electrical fuse formation during a multiple patterning process
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Application No.: US16918053Application Date: 2020-07-01
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Publication No.: US11348870B2Publication Date: 2022-05-31
- Inventor: Jiehui Shu , Xiaoqiang Zhang , Haizhou Yin , Moosung M. Chae , Jinping Liu , Hui Zang
- Applicant: GLOBALFOUNDRIES U.S. Inc.
- Applicant Address: US CA Santa Clara
- Assignee: GLOBALFOUNDRIES U.S. Inc.
- Current Assignee: GLOBALFOUNDRIES U.S. Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Thompson Hine LLP
- Agent Anthony Canale
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/768 ; H01L23/525

Abstract:
Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.
Public/Granted literature
- US20200335435A1 ELECTRICAL FUSE FORMATION DURING A MULTIPLE PATTERNING PROCESS Public/Granted day:2020-10-22
Information query
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