Invention Grant
- Patent Title: Tagged memory operated at lower vmin in error tolerant system
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Application No.: US17012501Application Date: 2020-09-04
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Publication No.: US11360667B2Publication Date: 2022-06-14
- Inventor: Nitin Chawla , Giuseppe Desoli , Anuj Grover , Thomas Boesch , Surinder Pal Singh , Manuj Ayodhyawasi
- Applicant: STMICROELECTRONICS S.r.l. , STMicroelectronics International N.V.
- Applicant Address: IT Agrate Brianza; CH Geneva
- Assignee: STMICROELECTRONICS S.r.l.,STMicroelectronics International N.V.
- Current Assignee: STMICROELECTRONICS S.r.l.,STMicroelectronics International N.V.
- Current Assignee Address: IT Agrate Brianza; CH Geneva
- Agency: Seed IP Law Group LLP
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06N3/08

Abstract:
A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
Public/Granted literature
- US20210072894A1 TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM Public/Granted day:2021-03-11
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