Invention Grant
- Patent Title: Performing hybrid wear leveling operations based on a sub-total write counter
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Application No.: US17114380Application Date: 2020-12-07
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Publication No.: US11360672B2Publication Date: 2022-06-14
- Inventor: Fangfang Zhu , Jiangli Zhu , Ning Chen , Ying Yu Tai
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/10

Abstract:
Data is copied, to a first group of data blocks in a first plurality of groups of unmapped data blocks, from a second group of data blocks in a second plurality of groups of mapped data blocks. Upon copying data to the first group of data blocks from the second group of data blocks, the first group of data blocks is included in the second plurality of groups of mapped data blocks. Upon including the first group of data blocks in the second plurality of groups of mapped data blocks, a wear leveling operation is performed on the first group of data blocks, wherein performing the wear leveling operation comprises determining a base address of the first group of data blocks, the base address indicating a location at which the first group of data blocks begins. A request to access subsequent data at a logical address associated with a data block included in the first group of data blocks is received. A physical address based on the base address of the first group of data blocks and the logical address is determined. The subsequent data is accessed at the first group of data blocks based on the physical address.
Public/Granted literature
- US20210089218A1 PERFORMING HYBRID WEAR LEVELING OPERATIONS BASED ON A SUB-TOTAL WRITE COUNTER Public/Granted day:2021-03-25
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