中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

125 records (took 0.028 seconds)

    Performing hybrid wear leveling operations based on a sub-total write counter
    3.
    发明授权
    Performing hybrid wear leveling operations based on a sub-total write counter 有权

    公开(公告)号：US11681442B2

    公开(公告)日：2023-06-20

    申请号：US17839293

    申请日：2022-06-13

    Applicant: Micron Technology, Inc.

    Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ning Chen ,  Ying Yu Tai

    IPC: G06F3/06 ,  G06F12/10

    CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0673 ,  G06F12/10 ,  G06F2212/1036 ,  G06F2212/1044

    Abstract: An example method may include performing a first wear leveling operation on a group of data blocks based on a write counter associated with the group of data blocks, wherein the first wear leveling operation comprises including the group of data blocks in a plurality of groups of mapped data blocks, responsive to including the group of data blocks in the plurality of groups of mapped data blocks, performing a second wear leveling operation on the group of data blocks, wherein performing the second wear leveling operation comprises determining a base address of the group of data blocks, the base address indicating a location at which the group of data blocks begins, and accessing a data block in the group of data blocks based on the base address of the group of data blocks and a logical address associated with the data block.

    Management of write operations in a non-volatile memory device using a variable pre-read voltage level
    4.
    发明授权
    Management of write operations in a non-volatile memory device using a variable pre-read voltage level 有权

    公开(公告)号：US11620085B2

    公开(公告)日：2023-04-04

    申请号：US17506246

    申请日：2021-10-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Ying Yu Tai ,  Jiangli Zhu

    IPC: G06F3/06

    Abstract: A processing device, operatively coupled with a memory device, performs operations including receiving a write request from a host system at a first time, the write request identifying first data to be stored in a segment of the memory device, determining whether a pre-read voltage level of the write request satisfies a pre-read voltage level criterion pertaining to a write-to-write time interval for the segment, wherein the write-to-write time interval is defined by the first time and a second time corresponding to a last time at which the segment was written, and responsive to determining that the pre-read voltage level satisfies the pre-read voltage level criterion pertaining to the write-to-write time interval, performing a pre-read operation on the segment using the pre-read voltage level to determine second data currently stored in the segment.

    Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller
    5.
    发明授权
    Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller 有权

    公开(公告)号：US11567817B2

    公开(公告)日：2023-01-31

    申请号：US17335433

    申请日：2021-06-01

    Applicant: Micron Technology, Inc.

    Inventor： Samir Mittal ,  Ying Yu Tai ,  Cheng Yuan Wu

    IPC: G06F11/00 ,  G06F11/07 ,  G06F13/12 ,  G06F13/16

    Abstract: A processing device can determine a configuration parameter based on a memory type of a memory component that is managed by a memory system controller. The processing device can receive data from a host system. The processing device can generate, by performing a memory operation using the configuration parameter, an instruction based on the data. The processing device can identify a sequencer of a plurality of sequencers that are collocated, within a single package external to the memory system controller, wherein each sequencer of the plurality of sequencers interfaces with a respective memory component. The processing device can send the instruction to the sequencer.

    MAINTENANCE OPERATIONS FOR MEMORY DEVICES
    6.
    发明申请
    MAINTENANCE OPERATIONS FOR MEMORY DEVICES 有权

    公开(公告)号：US20220404969A1

    公开(公告)日：2022-12-22

    申请号：US17859816

    申请日：2022-07-07

    Applicant: Micron Technology, Inc.

    Inventor： Ning Chen ,  Jiangli Zhu ,  Fangfang Zhu ,  Ying Yu Tai

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for performing an access operation on a memory cell, incrementing a value of a first counter based on performing the access operation on the memory cell, determining that the incremented value of the first counter satisfies a threshold, incrementing a value of a second counter based on determining that the incremented value of the first counter satisfies the threshold, and performing a maintenance operation on the memory cell based on determining that the incremented value of the first counter satisfies the threshold are described.

    Performing hybrid wear leveling operations based on a sub-total write counter
    7.
    发明授权
    Performing hybrid wear leveling operations based on a sub-total write counter 有权

    公开(公告)号：US11360672B2

    公开(公告)日：2022-06-14

    申请号：US17114380

    申请日：2020-12-07

    Applicant: Micron Technology, Inc.

    Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ning Chen ,  Ying Yu Tai

    IPC: G06F3/06 ,  G06F12/10

    Abstract: Data is copied, to a first group of data blocks in a first plurality of groups of unmapped data blocks, from a second group of data blocks in a second plurality of groups of mapped data blocks. Upon copying data to the first group of data blocks from the second group of data blocks, the first group of data blocks is included in the second plurality of groups of mapped data blocks. Upon including the first group of data blocks in the second plurality of groups of mapped data blocks, a wear leveling operation is performed on the first group of data blocks, wherein performing the wear leveling operation comprises determining a base address of the first group of data blocks, the base address indicating a location at which the first group of data blocks begins. A request to access subsequent data at a logical address associated with a data block included in the first group of data blocks is received. A physical address based on the base address of the first group of data blocks and the logical address is determined. The subsequent data is accessed at the first group of data blocks based on the physical address.

    Biased sampling methodology for wear leveling
    8.
    发明授权
    Biased sampling methodology for wear leveling 有权

    公开(公告)号：US11341036B2

    公开(公告)日：2022-05-24

    申请号：US16921479

    申请日：2020-07-06

    Applicant: Micron Technology, Inc.

    Inventor： Ying Yu Tai ,  Jiangli Zhu

    IPC: G06F12/02 ,  G06F12/06

    Abstract: A system includes a memory device and a processing device, coupled to the memory device. The processing device is to sample a first subset of data units from a set of data units of the memory device using a biased sampling process that increases a probability of sampling particular data units from the set of data units based on one or more characteristics associated with the particular data units. The processing device is to identify a first candidate data unit from the first subset of data units and perform a wear leveling operation in view of the first candidate data unit.

    Maintaining data consistency in a memory subsystem that uses hybrid wear leveling operations
    9.
    发明授权
    Maintaining data consistency in a memory subsystem that uses hybrid wear leveling operations 有权

    公开(公告)号：US11307983B2

    公开(公告)日：2022-04-19

    申请号：US17247373

    申请日：2020-12-09

    Applicant: Micron Technology, Inc.

    Inventor： Ning Chen ,  Jiangli Zhu ,  Ying Yu Tai

    IPC: G06F12/02 ,  G06F3/06

    Abstract: A processing device in a memory sub-system maintains a mapping data structure to track data movements from a plurality of data management units associated with a media management operation on a memory device. The processing device further uses a first indicator and a second indicator of a plurality of indicators to indicate which data of data management units of a source group of data management units have been copied to a destination group of data management units during the media management operation. Data located in data management units preceding the first indicator have been copied to data management units of the destination group of data management units. Data located in data management units associated with the first indicator and the second indicator or between the first indicator and the second indicator are either copied to data management units of the destination group of data management units or remain located in data management units of the source group of data management units. Data located in data management units subsequent to the second indicator remain located in data management units of the source group of data management units and have not been copied to the destination group of data management units.

    Read voltage management based on write-to-read time difference
    10.
    发明授权
    Read voltage management based on write-to-read time difference 有权

    公开(公告)号：US11119697B2

    公开(公告)日：2021-09-14

    申请号：US16510567

    申请日：2019-07-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Ying Yu Tai ,  Jiangli Zhu

    IPC: G06F12/00 ,  G06F3/06 ,  G11C7/10 ,  G11C7/22

    Abstract: A request can be received to perform a read operation to retrieve data at a memory sub-system. A time to perform the read operation can be determined. A time a write operation was performed to store the data at the memory sub-system can be determined. An amount of time that has elapsed since the time the performance of the write operation until the time to perform the read operation can be determined. A read voltage from a plurality of read voltages can be selected based on the amount of time that has elapsed. The read operation can be performed to retrieve the data by using the read voltage.

Patent Agency Ranking