Invention Grant
- Patent Title: Method and apparatus for performing redundancy analysis of a semiconductor device
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Application No.: US16933514Application Date: 2020-07-20
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Publication No.: US11360840B2Publication Date: 2022-06-14
- Inventor: Atishay , Prasanth B
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: IN202041002300 20200120
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/07

Abstract:
Embodiments of present disclosure relates to method and apparatus for performing redundancy analysis of a semiconductor device. For the redundancy analysis, plurality of banks in the semiconductor device is classified to be associated with a cluster from plurality of clusters. The classification is based on one or more attributes associated with the plurality of banks. Further, at least one cluster parameter for the plurality of clusters and at least one bank parameter for the plurality of banks, is determined. One or more algorithms is mapped with the plurality of clusters, based on the at least one cluster parameter and the at least one bank parameter. The redundancy analysis of at least one bank in the plurality of clusters is performed based on the mapping.
Public/Granted literature
- US20210224146A1 METHOD AND APPARATUS FOR PERFORMING REDUNDANCY ANALYSIS OF A SEMICONDUCTOR DEVICE Public/Granted day:2021-07-22
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