METHOD AND APPARATUS FOR PERFORMING REDUNDANCY ANALYSIS OF A SEMICONDUCTOR DEVICE

    公开(公告)号:US20210224146A1

    公开(公告)日:2021-07-22

    申请号:US16933514

    申请日:2020-07-20

    Inventor: Atishay Prasanth B

    Abstract: Embodiments of present disclosure relates to method and apparatus for performing redundancy analysis of a semiconductor device. For the redundancy analysis, plurality of banks in the semiconductor device is classified to be associated with a cluster from plurality of clusters. The classification is based on one or more attributes associated with the plurality of banks. Further, at least one cluster parameter for the plurality of clusters and at least one bank parameter for the plurality of banks, is determined. One or more algorithms is mapped with the plurality of clusters, based on the at least one cluster parameter and the at least one bank parameter. The redundancy analysis of at least one bank in the plurality of clusters is performed based on the mapping.

    Method and apparatus for performing redundancy analysis of a semiconductor device

    公开(公告)号:US11360840B2

    公开(公告)日:2022-06-14

    申请号:US16933514

    申请日:2020-07-20

    Inventor: Atishay Prasanth B

    Abstract: Embodiments of present disclosure relates to method and apparatus for performing redundancy analysis of a semiconductor device. For the redundancy analysis, plurality of banks in the semiconductor device is classified to be associated with a cluster from plurality of clusters. The classification is based on one or more attributes associated with the plurality of banks. Further, at least one cluster parameter for the plurality of clusters and at least one bank parameter for the plurality of banks, is determined. One or more algorithms is mapped with the plurality of clusters, based on the at least one cluster parameter and the at least one bank parameter. The redundancy analysis of at least one bank in the plurality of clusters is performed based on the mapping.

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