Invention Grant
- Patent Title: Enhancement for activation and deactivation of memory address regions
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Application No.: US16952813Application Date: 2020-11-19
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Publication No.: US11379367B2Publication Date: 2022-07-05
- Inventor: Nicola Colella , Antonino Pollio , Hua Tan
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0802 ; G06F12/02

Abstract:
Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.
Public/Granted literature
- US20220156185A1 ENHANCEMENT FOR ACTIVATION AND DEACTIVATION OF MEMORY ADDRESS REGIONS Public/Granted day:2022-05-19
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