A memory device including a memory cell area having a plurality of memory cells, and a peripheral circuit area including peripheral circuits configured to control the memory cells, the peripheral circuits connected to the memory cells by at least a portion of bit lines, word lines, and select lines may be provided. The peripheral circuits may include a reference voltage generator configured to output at least one reference voltage in response to control data of a control logic. The reference voltage generator may include a first resistor chain including first resistors connected in series between a first power node and a second power node, a second resistor chain including second resistors connected in series between the first power node and the second power node, and a plurality of decoders connected to the first resistor chain and the second resistor chain.