Invention Grant
- Patent Title: Systems and methods for reducing blocking artifacts
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Application No.: US16831084Application Date: 2020-03-26
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Publication No.: US11432017B2Publication Date: 2022-08-30
- Inventor: Mangesh Devidas Sadafale
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Charles F. Koch; Charles A. Brill; Frank D. Cimino
- Priority: IN2120/CHE/2011 20110622
- Main IPC: H04N19/00
- IPC: H04N19/00 ; H04N19/86 ; H04N19/159 ; H04N19/176 ; H04N19/117 ; H04N19/14 ; H04N19/80

Abstract:
Several methods and systems for reducing blocking artifacts are disclosed. In an embodiment, the method includes receiving a pair of adjacent blocks having an edge being positioned between the adjacent blocks. The pair of adjacent blocks is associated with one or more coding blocks. The one or more coding blocks comprise one or more coding information associated with the coding of the pair of adjacent blocks. The method also includes conducting a determination of whether the pair of adjacent blocks is coded in a skip-mode based on the one or more coding information. The edge is filtered based on the determination. Filtering the edge comprises disabling a de-blocking filtering of the edge based on a determination that the pair of adjacent blocks is coded in the skip-mode; and enabling the de-blocking filtering of the edge based on determination that the pair of adjacent blocks is not associated with the skip-mode.
Public/Granted literature
- US20200228845A1 SYSTEMS AND METHODS FOR REDUCING BLOCKING ARTIFACTS Public/Granted day:2020-07-16
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