Invention Grant
- Patent Title: Integrated fan-out packaging
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Application No.: US17122616Application Date: 2020-12-15
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Publication No.: US11437327B2Publication Date: 2022-09-06
- Inventor: Han-Ping Pu , Hsiao-Wen Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/00 ; H01L21/683 ; H01L21/768 ; H01L23/31 ; H01L21/56 ; H01L23/498

Abstract:
The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.
Public/Granted literature
- US20210098385A1 INTEGRATED FAN-OUT PACKAGING Public/Granted day:2021-04-01
Information query
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