Invention Grant
- Patent Title: Machine learning accelerator
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Application No.: US16682466Application Date: 2019-11-13
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Publication No.: US11443174B2Publication Date: 2022-09-13
- Inventor: Daniele Garbin , Simone Lavizzari
- Applicant: IMEC VZW , Katholieke Universiteit Leuven, KU LEUVEN R&D
- Applicant Address: BE Leuven; BE Leuven
- Assignee: IMEC VZW,Katholieke Universiteit Leuven, KU LEUVEN R&D
- Current Assignee: IMEC VZW,Katholieke Universiteit Leuven, KU LEUVEN R&D
- Current Assignee Address: BE Leuven; BE Leuven
- Agency: McDonnell Boehnen Hulbert & Berghoff LLP
- Priority: EP18205919 20181113
- Main IPC: G06N3/063
- IPC: G06N3/063 ; G11C13/00 ; G11C16/26

Abstract:
A neural network circuit for providing a threshold weighted sum of input signals comprises at least two arrays of transistors with programmable threshold voltage, each transistor storing a synaptic weight as a threshold voltage and having a control electrode for receiving an activation input signal. Additionally, for each array of transistors, a reference network associated therewith, which provides a reference signal to be combined with the positive or negative weight current components of the transistors of the associated array, the reference signal having opposite sign compared to the weight current components of the associated array, thereby providing the threshold of the weighted sums of the currents. Further, at least one bitline is configured to receive the combined positive and/or negative current components, each combined with their associated reference signals.
Public/Granted literature
- US20200151550A1 Machine Learning Accelerator Public/Granted day:2020-05-14
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