Invention Grant
- Patent Title: Wafer-level stacked die structures and associated systems and methods
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Application No.: US16721670Application Date: 2019-12-19
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Publication No.: US11444059B2Publication Date: 2022-09-13
- Inventor: Chih Yuan Chang
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/31 ; H01L23/498 ; H01L23/00 ; H01L21/56 ; H01L25/00

Abstract:
A stacked die structure for a semiconductor device generally includes a primary level with a first die formed in a wafer, and a second level with a second die coupled to the first die. A third level includes a third die coupled to the second die. The levels have conductive first, second, and third interconnects, respectively, extending from active sides of the dies and may be bonded prior to stacking the dies. The dies may be stacked in an offset or rotated position relative to each other such that the interconnects extend beyond each of the other dies to contact a redistribution layer that forms electrical connections with external components. In some configurations, a fourth level having a fourth die and a conductive fourth interconnect is coupled to the third die and positioned laterally offset from the third die such that the third interconnect extends beyond the fourth die.
Public/Granted literature
- US20210193621A1 WAFER-LEVEL STACKED DIE STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS Public/Granted day:2021-06-24
Information query
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