公开(公告)号：US12125826B2

公开(公告)日：2024-10-22

申请号：US17819036

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Chih Yuan Chang

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/32 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2225/06548 ,  H01L2225/06562

Abstract: A stacked die structure for a semiconductor device generally includes a primary level with a first die formed in a wafer, and a second level with a second die coupled to the first die. A third level includes a third die coupled to the second die. The levels have conductive first, second, and third interconnects, respectively, extending from active sides of the dies and may be bonded prior to stacking the dies. The dies may be stacked in an offset or rotated position relative to each other such that the interconnects extend beyond each of the other dies to contact a redistribution layer that forms electrical connections with external components. In some configurations, a fourth level having a fourth die and a conductive fourth interconnect is coupled to the third die and positioned laterally offset from the third die such that the third interconnect extends beyond the fourth die.

公开(公告)号：US20250022852A1

公开(公告)日：2025-01-16

申请号：US18901972

申请日：2024-09-30

Applicant: Micron Technology, Inc.

Inventor： Chih Yuan Chang

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A stacked die structure for a semiconductor device generally includes a primary level with a first die formed in a wafer, and a second level with a second die coupled to the first die. A third level includes a third die coupled to the second die. The levels have conductive first, second, and third interconnects, respectively, extending from active sides of the dies and may be bonded prior to stacking the dies. The dies may be stacked in an offset or rotated position relative to each other such that the interconnects extend beyond each of the other dies to contact a redistribution layer that forms electrical connections with external components. In some configurations, a fourth level having a fourth die and a conductive fourth interconnect is coupled to the third die and positioned laterally offset from the third die such that the third interconnect extends beyond the fourth die.

公开(公告)号：US20210193621A1

公开(公告)日：2021-06-24

申请号：US16721670

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Chih Yuan Chang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

Abstract: A stacked die structure for a semiconductor device generally includes a primary level with a first die formed in a wafer, and a second level with a second die coupled to the first die. A third level includes a third die coupled to the second die. The levels have conductive first, second, and third interconnects, respectively, extending from active sides of the dies and may be bonded prior to stacking the dies. The dies may be stacked in an offset or rotated position relative to each other such that the interconnects extend beyond each of the other dies to contact a redistribution layer that forms electrical connections with external components. In some configurations, a fourth level having a fourth die and a conductive fourth interconnect is coupled to the third die and positioned laterally offset from the third die such that the third interconnect extends beyond the fourth die.

公开(公告)号：US20220384393A1

公开(公告)日：2022-12-01

申请号：US17819036

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Chih Yuan Chang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A stacked die structure for a semiconductor device generally includes a primary level with a first die formed in a wafer, and a second level with a second die coupled to the first die. A third level includes a third die coupled to the second die. The levels have conductive first, second, and third interconnects, respectively, extending from active sides of the dies and may be bonded prior to stacking the dies. The dies may be stacked in an offset or rotated position relative to each other such that the interconnects extend beyond each of the other dies to contact a redistribution layer that forms electrical connections with external components. In some configurations, a fourth level having a fourth die and a conductive fourth interconnect is coupled to the third die and positioned laterally offset from the third die such that the third interconnect extends beyond the fourth die.

公开(公告)号：US11444059B2

公开(公告)日：2022-09-13

申请号：US16721670

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Chih Yuan Chang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A stacked die structure for a semiconductor device generally includes a primary level with a first die formed in a wafer, and a second level with a second die coupled to the first die. A third level includes a third die coupled to the second die. The levels have conductive first, second, and third interconnects, respectively, extending from active sides of the dies and may be bonded prior to stacking the dies. The dies may be stacked in an offset or rotated position relative to each other such that the interconnects extend beyond each of the other dies to contact a redistribution layer that forms electrical connections with external components. In some configurations, a fourth level having a fourth die and a conductive fourth interconnect is coupled to the third die and positioned laterally offset from the third die such that the third interconnect extends beyond the fourth die.