Invention Grant
- Patent Title: Phase-locked loop circuit having linear voltage-domain time-to-digital converter with output subrange
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Application No.: US17488339Application Date: 2021-09-29
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Publication No.: US11456750B2Publication Date: 2022-09-27
- Inventor: Ang-Sheng Lin , Chun-Wei Chang , Tzu-Chan Chueh
- Applicant: MEDIATEK INC.
- Applicant Address: TW Hsin-Chu
- Assignee: MEDIATEK INC.
- Current Assignee: MEDIATEK INC.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: H03L7/093
- IPC: H03L7/093 ; H03L7/081 ; H03L7/089 ; H03L7/099

Abstract:
A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.
Public/Granted literature
- US20220149849A1 Phase-Locked Loop Circuit having Linear Voltage-domain Time-to-Digital Converter with Output Subrange Public/Granted day:2022-05-12
Information query
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