A semiconductor package includes a sub semiconductor package disposed over a substrate. The sub semiconductor package includes a sub semiconductor chip with chip pads on its upper surface, a sub molding layer that surrounds the sub semiconductor chip, and a redistribution conductive layer that is connected to each of the chip pads and extends over an upper surface of the sub molding layer. The redistribution conductive layer includes a signal redistribution conductive layer that extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion and a power redistribution conductive layer with a length that is shorter than a length of the signal redistribution conductive layer. The semiconductor package also includes a sub signal interconnector, sub power interconnector, and at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate or the sub semiconductor chip.