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    Semiconductor package including stacked semiconductor chips
    2.
    发明授权
    Semiconductor package including stacked semiconductor chips 有权

    公开(公告)号：US12009344B2

    公开(公告)日：2024-06-11

    申请号：US17200063

    申请日：2021-03-12

    Applicant: SK hynix Inc.

    Inventor： Jin Kyoung Park

    IPC: H01L25/065 ,  H01L23/00

    CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

    Abstract: A semiconductor package including: a base layer; a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including a plurality of semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack and chip identification pads for identifying the plurality of semiconductor chips in each of the first and second chip stacks; a first inter-chip wire and a second inter-chip wire connecting power-applied ones of the chip identification pads of the plurality of semiconductor chips of the first and second chip stacks; a first stack wire and second stack wire connecting the chip identification pad of a lowermost semiconductor chip of the first and second chip stacks to the base layer.

    Semiconductor package including capacitor
    3.
    发明授权
    Semiconductor package including capacitor 有权

    公开(公告)号：US11270958B2

    公开(公告)日：2022-03-08

    申请号：US16991683

    申请日：2020-08-12

    Applicant: SK hynix Inc.

    Inventor： Ju Il Eom ,  Jin Kyoung Park ,  Han Jun Bae

    IPC: H01L23/64 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L49/02

    Abstract: A semiconductor package includes: a sub semiconductor package disposed over a substrate, the sub semiconductor package including a sub semiconductor chip which has chip pads on its upper surface, a molding layer which surrounds side surfaces of the sub semiconductor chip, and a redistribution layer formed over the sub semiconductor chip and the molding layer, the redistribution layer including redistribution conductive layers which are connected to the chip pads of the sub semiconductor chip and extend onto edges of the molding layer while having redistribution pads on their end portions; first sub package interconnectors connected to the redistribution pads to electrically connect the sub semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion, the first and second electrodes having upper surfaces which are connected to the redistribution conductive layers, respectively.

    Semiconductor packages having asymmetric chip stack structure
    4.
    发明授权
    Semiconductor packages having asymmetric chip stack structure 有权

    公开(公告)号：US10217722B2

    公开(公告)日：2019-02-26

    申请号：US15970526

    申请日：2018-05-03

    Applicant: SK hynix Inc.

    Inventor： Jin Kyoung Park

    IPC: H01L23/49 ,  H01L25/065

    Abstract: A semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall. The first protrusion corner of the first chip stack may protrude toward the second chip stack.

    Semiconductor package including stacked semiconductor chips
    6.
    发明授权
    Semiconductor package including stacked semiconductor chips 有权

    公开(公告)号：US11462511B2

    公开(公告)日：2022-10-04

    申请号：US17070174

    申请日：2020-10-14

    Applicant: SK hynix Inc.

    Inventor： Ju Il Eom ,  Jin Kyoung Park

    IPC: H01L25/065

    Abstract: A semiconductor package includes a sub semiconductor package disposed over a substrate. The sub semiconductor package includes a sub semiconductor chip with chip pads on its upper surface, a sub molding layer that surrounds the sub semiconductor chip, and a redistribution conductive layer that is connected to each of the chip pads and extends over an upper surface of the sub molding layer. The redistribution conductive layer includes a signal redistribution conductive layer that extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion and a power redistribution conductive layer with a length that is shorter than a length of the signal redistribution conductive layer. The semiconductor package also includes a sub signal interconnector, sub power interconnector, and at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate or the sub semiconductor chip.

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