- 专利标题: Pulse width modulation circuit with reduced minimum on-time
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申请号: US16935408申请日: 2020-07-22
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公开(公告)号: US11482995B1公开(公告)日: 2022-10-25
- 发明人: Jindrich Svorc , Jens Masuch
- 申请人: Dialog Semiconductor (UK) Limited
- 申请人地址: GB London
- 专利权人: Dialog Semiconductor (UK) Limited
- 当前专利权人: Dialog Semiconductor (UK) Limited
- 当前专利权人地址: GB London
- 代理机构: Saile Ackerman LLC
- 代理商 Stephen B. Ackerman
- 主分类号: H03K7/08
- IPC分类号: H03K7/08 ; H02M3/156 ; H02M1/00
摘要:
A pulse width modulator PWM circuit and a corresponding method are presented. The PWM circuit receives a control signal and a clock signal. The PWM circuit generates an output signal based on the control signal and the clock signal. The output signal has a first or second signal value. The PWM circuit has a delay circuit to generate, by delaying the clock signal by a delay period, a first enable signal for setting the output signal to the first signal value. The PWM circuit has a ramp generator to generate a ramp signal based on the clock signal. The PWM circuit has a comparator to generate, by comparing the control signal with the ramp signal, a second enable signal for setting the output signal to the second signal value. By delaying the clock signal by the delay period, a minimum on-time of the output signal may be reduced.
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