Pulse width modulation circuit with reduced minimum on-time
摘要:
A pulse width modulator PWM circuit and a corresponding method are presented. The PWM circuit receives a control signal and a clock signal. The PWM circuit generates an output signal based on the control signal and the clock signal. The output signal has a first or second signal value. The PWM circuit has a delay circuit to generate, by delaying the clock signal by a delay period, a first enable signal for setting the output signal to the first signal value. The PWM circuit has a ramp generator to generate a ramp signal based on the clock signal. The PWM circuit has a comparator to generate, by comparing the control signal with the ramp signal, a second enable signal for setting the output signal to the second signal value. By delaying the clock signal by the delay period, a minimum on-time of the output signal may be reduced.
信息查询
0/0