Invention Grant
- Patent Title: Pipeline including separate hardware data paths for different instruction types
-
Application No.: US16860842Application Date: 2020-04-28
-
Publication No.: US11494192B2Publication Date: 2022-11-08
- Inventor: Jiasheng Chen , YunXiao Zou , Bin He , Angel E. Socarras , QingCheng Wang , Wei Yuan , Michael Mantor
- Applicant: ADVANCED MICRO DEVICES, INC. , ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.
- Applicant Address: US CA Santa Clara; CN Shanghai
- Assignee: ADVANCED MICRO DEVICES, INC.,ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.
- Current Assignee: ADVANCED MICRO DEVICES, INC.,ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.
- Current Assignee Address: US CA Santa Clara; CN Shanghai
- Priority: CN201610920423.4 20161021
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/30 ; G06F15/80 ; G06F15/76

Abstract:
A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.
Public/Granted literature
- US20200293329A1 PIPELINE INCLUDING SEPARATE HARDWARE DATA PATHS FOR DIFFERENT INSTRUCTION TYPES Public/Granted day:2020-09-17
Information query