发明授权
- 专利标题： Pipeline including separate hardware data paths for different instruction types
-
申请号： US16860842申请日： 2020-04-28
-
公开(公告)号： US11494192B2公开(公告)日： 2022-11-08
- 发明人: Jiasheng Chen , YunXiao Zou , Bin He , Angel E. Socarras , QingCheng Wang , Wei Yuan , Michael Mantor
- 申请人： ADVANCED MICRO DEVICES, INC. , ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.
- 申请人地址： US CA Santa Clara; CN Shanghai
- 专利权人： ADVANCED MICRO DEVICES, INC.,ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.
- 当前专利权人： ADVANCED MICRO DEVICES, INC.,ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.
- 当前专利权人地址： US CA Santa Clara; CN Shanghai
- 优先权： CN201610920423.4 20161021
- 主分类号： G06F9/38
- IPC分类号： G06F9/38 ; G06F9/30 ; G06F15/80 ; G06F15/76
摘要：
A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.
公开/授权文献
信息查询
