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公开(公告)号：US12237286B2
公开(公告)日：2025-02-25
申请号：US18455960
申请日：2023-08-25
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Rahul Agarwal
IPC: H01L23/00 , H01L23/528
Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.
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公开(公告)号：US12237026B1
公开(公告)日：2025-02-25
申请号：US17982382
申请日：2022-11-07
Applicant: Advanced Micro Devices, Inc.
Inventor： Vaibhav Anand Srivastava , Pankaj Kumar
Abstract: The disclosed computer-implemented method relating to read-only memory can include (i) asserting a column select signal to select a particular column within a column mux read-only memory, (ii) forwarding, in response to asserting the column select signal, a bit value stored at that particular column to a gate of a transistor that connects a first stage local bitline to a second stage local bitline, and (iii) forwarding an inversion of the bit value to the second stage local bitline through the drain of the transistor for local bitline sensing. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US12236134B2
公开(公告)日：2025-02-25
申请号：US17953723
申请日：2022-09-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Mahzabeen Islam , Shaizeen Dilawarhusen Aga , Johnathan Robert Alsop , Mohamed Assem Abd ElMohsen Ibrahim , Nuwan S Jayasena
IPC: G06F3/06
Abstract: In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory component to perform operations that access the second bank. A next row of the first bank that is to be accessed by the processing in memory component is identified. Further, a precharge command is scheduled to close a first row of the first bank and an activate command is scheduled to open the next row of the first bank in parallel with execution of the second stream of commands.
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公开(公告)号：US12229570B2
公开(公告)日：2025-02-18
申请号：US17952270
申请日：2022-09-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Bin He , Michael John Mantor , Brian Emberling , Liang Huang , Chao Liu
Abstract: Block data load with transpose techniques are described. In one example, an input is received, at a control unit, specifying an instruction to load a block of data to at least one memory module using a transpose operation. Responsive to the receiving the input by the control unit, the block of data is caused to be loaded to the at least one memory module by transposing the block of data to form a transposed block of data and storing the transposed block of data in the at least one memory.
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公开(公告)号：US12217061B2
公开(公告)日：2025-02-04
申请号：US18309536
申请日：2023-04-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Maxim V. Kazakov
Abstract: Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including identifying that no instructions are available for which sufficient processing resources exist for execution together within the processing lane; and in response to the second identifying, executing an instruction independently of any other instruction.
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Patent Agency Ranking
公开(公告)号：US20250037750A1
公开(公告)日：2025-01-30
申请号：US18783900
申请日：2024-07-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Indrani Paul , Benjamin Tsien , James R. Magro
IPC: G11C11/4074 , G11C5/14 , G11C11/406
Abstract: The disclosed systems and methods include a control circuit for entering a low power state of a memory by preserving a context of the memory's controller and power gating the memory's physical layer. The context can be saved to a non-volatile memory device or by keeping a retention supply voltage to a register of the memory controller. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US20250028554A1
公开(公告)日：2025-01-23
申请号：US18909132
申请日：2024-10-08
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Anthony GUTIERREZ , Sooraj PUTHOOR
Abstract: A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.
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公开(公告)号：US20250028010A1
公开(公告)日：2025-01-23
申请号：US18355011
申请日：2023-07-19
Applicant: Advanced Micro Devices, Inc.
Inventor： ChaiLin Yu , YanHe Qi , JiJun Shi
IPC: G01R31/66
Abstract: A computer-implemented method for abnormal power connection detection can include receiving, by at least one processor, a power signal by a power connector and an additional power signal by an additional power connector. The method can additionally include performing, by the at least one processor, one or more measurements of the additional power signal. The method can also include carrying out, by the at least one processor, one or more response procedures based on the one or more measurements. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US12204908B2
公开(公告)日：2025-01-21
申请号：US15997344
申请日：2018-06-04
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Marius Evers , Douglas Williams , Ashok T. Venkatachar , Sudherssen Kalaiselvan
Abstract: A branch predictor predicts a first outcome of a first branch in a first block of instructions. Fetch logic fetches instructions for speculative execution along a first path indicated by the first outcome. Information representing a remainder of the first block is stored in response to the first predicted outcome being taken. In response to the first branch instruction being not taken, the branch predictor is restarted based on the remainder block. In some cases, entries corresponding to second blocks along speculative paths from the first block are accessed using an address of the first block as an index into a branch prediction structure. Outcomes of branch instructions in the second blocks are concurrently predicted using a corresponding set of instances of branch conditional logic and the predicted outcomes are used in combination with the remainder block to restart the branch predictor in response to mispredictions.
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公开(公告)号：US12204754B2
公开(公告)日：2025-01-21
申请号：US16959503
申请日：2018-09-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Kedarnath Balakrishnan , James Raymond Magro
Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.
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