Invention Grant
- Patent Title: Write interamble counter
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Application No.: US16834409Application Date: 2020-03-30
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Publication No.: US11495281B2Publication Date: 2022-11-08
- Inventor: William C. Waldrop , Daniel B. Penney
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/4076 ; G06F11/10 ; G11C11/4096 ; G11C11/4093

Abstract:
Systems and methods are provided that provide protection from undesired latching that may be caused by indeterminate interamble periods in an input/output data strobe (DQS) signal. Interamble compensation circuitry selectively filters out interamble states of the DQS signal to reduce provision of interamble signals to downstream components that use the DQS signal to identify data latching times.
Public/Granted literature
- US20210304809A1 WRITE INTERAMBLE COUNTER Public/Granted day:2021-09-30
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