Methods and systems for verifying a hardware design for a multi-stage component is stall independent. The multi-stage component is configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled by a set of one or more enable signals. The method comprises: for each stage of the plurality of stages from the second stage to the last stage: (a) verifying that a relevant portion of the output data of an instantiation of the hardware design is the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs; and (b) verifying that the relevant portion of the output data of an instantiation of the hardware design is the same if the instantiation is in the same state (i) when that stage is enabled in a cycle and any subsequent stages are enabled in subsequent cycles by a second minimal sequence of inputs and (ii) when that stage is stalled, then that stage is enabled in the next cycle and the subsequent stages are enabled in subsequent cycles by the second minimal sequence of inputs.