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公开(公告)号：US20230122999A1
公开(公告)日：2023-04-20
申请号：US18083492
申请日：2022-12-17
发明人： Xile Yang
摘要： Data structures, methods and primitive block generators for storing primitives in a graphics processing system. The method includes: receiving a primitive associated with state data that defines how the primitive is to be rendered; determining whether the state data associated with the received primitive matches state data for a current primitive block; and in response to determining that the state data for the received primitive matches the state data for the current primitive block: determining, based on one or more primitive section size constraints, whether the received primitive is to be added to a current primitive section of the current primitive block in a data store; in response to determining that the received primitive is to be added to the current primitive section, adding the received primitive to the current primitive section; and in response to determining that the received primitive is not to be added to the current primitive section: outputting the current primitive section; reconfiguring the data store to store a new primitive section for the current primitive block; and adding the received primitive to the new primitive section for the current primitive block.
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公开(公告)号：US20230120307A1
公开(公告)日：2023-04-20
申请号：US17953821
申请日：2022-09-27
发明人： Michael John Livesley , Ian King , Alistair Goudie
摘要： A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.
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公开(公告)号：US20230118937A1
公开(公告)日：2023-04-20
申请号：US17956778
申请日：2022-09-29
发明人： Szabolcs Csefalvay , James Imber , David Walton , Insu Yu
摘要： A method of rendering an image of a 3-D scene includes rendering a noisy image at a first resolution; obtaining one or more guide channels at the first resolution, and obtaining one or more corresponding guide channels at a second resolution. The second resolution may be the same resolution as, or a higher resolution than, the first resolution. For each of a plurality of local neighbourhoods, the method comprises: calculating the parameters of a model that approximates the noisy image as a function of the one or more guide channels (at the first resolution), and applying the calculated parameters to the one or more guide channels at the second resolution, to produce a denoised image at the second resolution.
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公开(公告)号：US20230114852A1
公开(公告)日：2023-04-13
申请号：US17956907
申请日：2022-09-30
发明人： Szabolcs Csefalvay , James Imber , David Walton , Insu Yu
摘要： A method of rendering an image of a 3-D scene includes rendering a noisy image and obtaining one or more guide channels. For each of a plurality of local neighborhoods, the method comprises: calculating the parameters of a model that approximates the noisy image as a function of the one or more guide channels, and applying the calculated parameters to produce a denoised image. At least one of (i) the noisy image, (ii) the one or more guide channels, and (iii) the denoised image, are stored in a quantized low-bitdepth format.
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公开(公告)号：US20230111909A1
公开(公告)日：2023-04-13
申请号：US17940104
申请日：2022-09-08
发明人： Christopher Notton
IPC分类号： G06T15/00
摘要： A multicore graphics processing unit (GPU) and a method of operating a GPU having at least a first core and a second core. A client driver writes a series of geometry commands in the command buffer, along with associated dependency data that indicates the extent to which correct execution of the geometry commands is dependent on the completion of execution of other commands. The first core reads a first geometry command from the command buffer and executes it. The second core reads a second geometry command from the command buffer. The second core determines that the second geometry command is not dependent on the results of the first geometry command, and, in response, executes the second geometry command.
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公开(公告)号：US20230097760A1
公开(公告)日：2023-03-30
申请号：US18075394
申请日：2022-12-05
发明人： Simon Nield , Yoong-Chert Foo , Adam de Grasse , Luca Iuliano
摘要： A method of activating scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state and checking, by an instruction controller, if a swap flag is set in the decoded instruction. If the swap flag in the decoded instruction is set, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state.
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公开(公告)号：US20230094013A1
公开(公告)日：2023-03-30
申请号：US17954511
申请日：2022-09-28
发明人： Michael John Livesley , Ian King , Alistair Goudie
摘要： A processor includes a blocking circuit between an upstream section and a downstream section of a hardware pipeline, and control circuitry which triggers the upstream section to process an upstream phase of a first task, with the blocking circuit in an open state whereby first data from the processing of the upstream phase of the first task passes through from the upstream section to be processed in a downstream phase of the first task. In response to detecting that the upstream section has finished processing the upstream phase of the first task, the control circuitry triggers the upstream section to start processing a second task while the downstream section is still processing the downstream phase of the first task, and switches the blocking circuit to a closed state blocking second data from the processing of the upstream phase of the second task passing to the downstream section.
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公开(公告)号：US20230090166A1
公开(公告)日：2023-03-23
申请号：US18071095
申请日：2022-11-29
发明人： Xile Yang , Robert Brigg , John W. Howson
摘要： Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods comprise: receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
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公开(公告)号：US20230089878A1
公开(公告)日：2023-03-23
申请号：US18071454
申请日：2022-11-29
发明人： Linling Zhang , Simon Fenney
IPC分类号： G06F3/06 , H04N19/645 , H04N19/34
摘要： A lossy method of compressing data, such as image data, which uses wrap-around wavelet compression is described. Each data value is divided into two parts and the first parts, which comprise the most significant bits from the data values, are compressed using wrap-around wavelet compression. Depending upon the target compression ratio and the compression ratio achieved by compressing just the first parts, none, one or more bits from the second parts, or from a data value derived from the second parts, may be appended to the compressed first parts. The method described may be lossy or may be lossless. A corresponding decompression method is also described.
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公开(公告)号：US20230088494A1
公开(公告)日：2023-03-23
申请号：US18070359
申请日：2022-11-28
发明人： Steven J. Fishwick , John W. Howson
摘要： A method and system for culling a patch of surface data from one or more tiles in a tile based computer graphics system. A rendering space is divided into a plurality of tiles and a patch of surface data read. Then, at least a portion of the patch is analysed to determine data representing a bounding depth value evaluated over at least one tile. This may comprise tessellating the patch of surface data to derive a plurality of tessellated primitives and analysing at least some of the tessellated primitives. For each tile within which the patch is located, the data representing the bounding depth value is then used to determine whether the patch is hidden in the tile, and at least a portion of the patch is rendered, if the patch is determined not to be hidden in at least one tile.
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