- 专利标题: Method and procedure for miniaturing a multi-layer PCB
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申请号: US17313073申请日: 2021-05-06
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公开(公告)号: US11523502B2公开(公告)日: 2022-12-06
- 发明人: Shaun Joseph Greaney , Robert Migliorino , Michael Liccone , Clint Smith
- 申请人: Veea Inc.
- 申请人地址: US NY New York
- 专利权人: Veea Inc.
- 当前专利权人: Veea Inc.
- 当前专利权人地址: US NY New York
- 代理机构: The Marbury Law Group, PLLC.
- 主分类号: H05K1/02
- IPC分类号: H05K1/02
摘要:
A multiple layer printed circuit board (PCB) in which the cores (or core layers) are removed and replaced with prepreg layers, which provide structure integrity for the PCB. Such a multi-layer PCB may include a plurality of layers that include a plurality of signal layers, a plurality of ground plane layers, a plurality of inner signal layers, and a single core substrate layer. Each layer in the plurality of layers may be separated from every other layer in the plurality of layers by at least one prepreg substrate layer.
公开/授权文献
- US20210352802A1 Method and Procedure for Miniaturing a Multi-layer PCB 公开/授权日:2021-11-11