Techniques are described for a compiler scheduling algorithm/routine that utilizes backtracking to generate an execution schedule for a neural network computation graph using a neural network compiler intermediate representation of hardware synchronization counters. The hardware synchronization counters may be referred to as physical barriers, hardware (HW) barriers, or barriers and their intermediate representations may be referred to as barrier tasks or barriers. Backtracking is utilized to prevent an available number of hardware barriers from being exceeded during performance of an execution schedule. An execution schedule may be a computation workload schedule for neural network inference applications. An execution schedule may also be a first in first out (FIFO) schedule.