Invention Grant
- Patent Title: Assessing performance of a hardware design using formal evaluation logic
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Application No.: US17184186Application Date: 2021-02-24
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Publication No.: US11531799B2Publication Date: 2022-12-20
- Inventor: Ashish Darbari , Iain Singleton
- Applicant: Imagination Technologies Limited
- Applicant Address: GB Kings Langley
- Assignee: Imagination Technologies Limited
- Current Assignee: Imagination Technologies Limited
- Current Assignee Address: GB Kings Langley
- Agency: Potomac Law Group, PLLC
- Agent Vincent M DeLuca
- Priority: GB1609255 20160525
- Main IPC: G06F30/3323
- IPC: G06F30/3323 ; G06F119/18 ; G06F11/30 ; G06F11/34 ; G06F11/36 ; G06F30/30 ; G06F30/39

Abstract:
A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.
Public/Granted literature
- US20210182463A1 ASSESSING PERFORMANCE OF A HARDWARE DESIGN USING FORMAL EVALUATION LOGIC Public/Granted day:2021-06-17
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