According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.