Multi-bit scan chain with error-bit generator

    公开(公告)号:US12068745B2

    公开(公告)日:2024-08-20

    申请号:US17462524

    申请日:2021-08-31

    申请人: Arm Limited

    摘要: Various implementations described herein are directed to a device having a scan chain that receives a multi-bit input, provides a multi-bit output, and provides a multi-bit multiplexer output based on the multi-bit input and the multi-bit output. The device may have an error-bit generator that receives the multi-bit multiplexer output, receives a portion of the multi-bit input, receives a portion of the multi-bit output, and provides an error-bit output based on the multi-bit multiplexer output, the portion of the multi-bit input, and the portion of the multi-bit output.

    Circuitry for memory address collision prevention

    公开(公告)号:US12066926B2

    公开(公告)日:2024-08-20

    申请号:US17861084

    申请日:2022-07-08

    申请人: Arm Limited

    IPC分类号: G06F12/02

    CPC分类号: G06F12/023 G06F2212/1008

    摘要: According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.

    Multi-input logic circuitry
    8.
    发明授权

    公开(公告)号:US11900039B2

    公开(公告)日:2024-02-13

    申请号:US17175639

    申请日:2021-02-13

    申请人: Arm Limited

    摘要: Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.

    Securitization of transportation units

    公开(公告)号:US11836791B2

    公开(公告)日:2023-12-05

    申请号:US17541080

    申请日:2021-12-02

    申请人: Circlesx LLC

    摘要: Various implementations directed to securitization of transportation units are provided. In one implementation, a method may include receiving origin location data and destination location data from a first user. The method may also include determining virtual hubs based on the origin location data and the destination location data. The method may further include determining virtual hub routes based on the virtual hubs. The method may additionally include receiving term specification data from the first user. The method may also include receiving attribute data for the virtual hub routes from the first user. The method may further include providing a transportation capacity exchange for transportation capacity units based on the virtual hub routes, the term specification data, and the attribute data. The method may additionally include transmitting a subset of the market depth data for the transportation capacity exchange to the first user.