Invention Grant
- Patent Title: Dual port memory cell with improved access resistance
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Application No.: US17491201Application Date: 2021-09-30
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Publication No.: US11532633B2Publication Date: 2022-12-20
- Inventor: Tushar Sharma , Tanmoy Roy , Shishir Kumar
- Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
- Applicant Address: NL Schiphol
- Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
- Current Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
- Current Assignee Address: NL Schiphol
- Agency: Seed Intellectual Property Law Group LLP
- Main IPC: G11C11/00
- IPC: G11C11/00 ; H01L27/11 ; G11C5/06 ; G11C11/412 ; H01L27/02 ; G11C8/16 ; G11C11/417

Abstract:
The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.
Public/Granted literature
- US20220020754A1 DUAL PORT MEMORY CELL WITH IMPROVED ACCESS RESISTANCE Public/Granted day:2022-01-20
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