Invention Grant
- Patent Title: Memory array with graded memory stack resistances
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Application No.: US17130215Application Date: 2020-12-22
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Publication No.: US11538860B2Publication Date: 2022-12-27
- Inventor: Fabio Pellizzer , Lorenzo Fratin , Hongmei Wang
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: H01L27/24
- IPC: H01L27/24 ; H01L45/00 ; H01L23/528 ; H01L21/66 ; H01L23/532
Abstract:
Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.
Public/Granted literature
- US20210111226A1 MEMORY ARRAY WITH GRADED MEMORY STACK RESISTANCES Public/Granted day:2021-04-15
Information query
IPC分类:
