公开(公告)号：US20220076770A1

公开(公告)日：2022-03-10

申请号：US17013089

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Nevil N. Gajera ,  Mingdong Cui ,  Fabio Pellizzer

IPC: G11C29/38

Abstract: An example apparatus can include a memory array and control circuitry. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The control circuitry can be configured to designate the first portion as active responsive to a determination that the first portion passed a performance test. The control circuitry can be configured to designate the second portion as inactive responsive to a determination that the second portion failed the performance test.

公开(公告)号：US11139034B1

公开(公告)日：2021-10-05

申请号：US16929884

申请日：2020-07-15

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Hongmei Wang ,  Mingdong Cui

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

Abstract: Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages across the memory cells based on a logic state of data to be written to the memory cells may be used. During a first interval of the write operation, a voltage may be applied across a memory cell based on a logic state of a data bit to be written to the memory cell. During a second interval of the write operation, a voltage may be applied across the memory cell based on an amount of charge conducted by the memory cell during the first interval.

公开(公告)号：US20210166746A1

公开(公告)日：2021-06-03

申请号：US16700948

申请日：2019-12-02

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Christina Papagianni ,  Hongmei Wang ,  Robert J. Gleixner

IPC: G11C11/409 ,  G11C11/408 ,  G11C11/56 ,  G11C7/22

Abstract: Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.

公开(公告)号：US10672500B2

公开(公告)日：2020-06-02

申请号：US16419885

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Rajesh Kamana ,  Hongmei Wang ,  Shawn D. Lyonsmith ,  Ervin T. Hill ,  Zengtao T. Liu ,  Marlon W. Hug

IPC: G11C13/00 ,  G11C29/50 ,  H01L21/66 ,  H01L45/00 ,  H01L27/24 ,  G11C29/56 ,  G11C29/04

Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.

公开(公告)号：US20190206489A1

公开(公告)日：2019-07-04

申请号：US15857188

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Luca Crespi ,  Debayan Mahalanabis ,  Fabio Pellizzer

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0073 ,  G11C2013/0076

Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.

公开(公告)号：US20150072512A1

公开(公告)日：2015-03-12

申请号：US14543063

申请日：2014-11-17

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang

IPC: H01L27/115 ,  H01L29/16

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/16 ,  H01L29/7889 ,  H01L29/7926

Abstract: Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material. Each of the levels of silicon is separated from an adjacent level of silicon by a level of the dielectric material. Strings of memory cells are formed along the levels of silicon. Additional apparatuses and methods are disclosed.

Abstract translation: 各种实施例包括包括沿半导体材料层形成的存储单元串的方法和装置。 一种这样的装置包括由许多级别的单晶硅和多种电介质材料构成的叠层。 硅层中的每一层都通过介电材料的水平与相邻硅层分离。 沿着硅层形成存储单元的串。 公开了附加的装置和方法。

公开(公告)号：US11710517B2

公开(公告)日：2023-07-25

申请号：US17569295

申请日：2022-01-05

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Christina Papagianni ,  Hongmei Wang ,  Robert J. Gleixner

IPC: G11C11/406 ,  G11C11/409 ,  G11C7/22 ,  G11C11/56 ,  G11C11/408

CPC classification number: G11C11/409 ,  G11C7/222 ,  G11C11/4082 ,  G11C11/5628

Abstract: Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.

公开(公告)号：US11538860B2

公开(公告)日：2022-12-27

申请号：US17130215

申请日：2020-12-22

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Lorenzo Fratin ,  Hongmei Wang

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L21/66 ,  H01L23/532

Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.

公开(公告)号：US20220328104A1

公开(公告)日：2022-10-13

申请号：US17227977

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Hongmei Wang ,  Robert J. Gleixner

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/30 ,  G06F7/58

Abstract: The present disclosure includes systems, apparatuses, and methods related to generating a random data value. For example, a first read operation may be performed on a memory cell programmed to a first state, wherein the first read operation is performed using a first read voltage that is within a predetermined threshold voltage distribution corresponding to the first state. A programming signal may be applied to the memory cell responsive to the first read operation resulting in a snapback event, wherein the programming signal is configured to place the memory cell in a second state. A second read operation may be performed to determine whether the memory cell is in the first state or the second state using a second read voltage that is between the predetermined threshold voltage distribution corresponding to the first state and a second threshold voltage distribution corresponding to the second state.

公开(公告)号：US20220130444A1

公开(公告)日：2022-04-28

申请号：US17569295

申请日：2022-01-05

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Christina Papagianni ,  Hongmei Wang ,  Robert J. Gleixner

IPC: G11C11/409 ,  G11C7/22 ,  G11C11/56 ,  G11C11/408

Abstract: Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.