A semiconductor memory device includes a memory cell array, a sense amplifier circuit and a random code generator. The memory cell array is divided into a plurality of sub array blocks arranged in a first direction and a second direction crossing the first direction. The sense amplifier circuit is arranged in the second direction with respect to the memory cell array, and includes a plurality of input/output (I/O) sense amplifiers. The random code generator generates a random code which is randomly determined based on a power stabilizing signal and an anti-fuse flag signal. A second group of I/O sense amplifiers selected from among a first group of I/O sense amplifiers performs a data I/O operation by data scrambling data bits of main data. The first group of I/O sense amplifiers correspond to a first group of sub array blocks accessed by an access address.